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? semiconductor component s industries, llc, 2016 1 publication order number : october 2016 - rev. p3 STK5Q4U362J-E/d this document contains information on a new product. specifications and information herein are subject to change without notice. STK5Q4U362J-E advance information intelligent power module (ipm) 600 v, 10 a the STK5Q4U362J-E is a fully-integrated inverter power stage consisting of a high-voltage driver, six igbt?s and a thermistor, suitable for driving permanent magnet synchronous (pmsm) motors, brushless- dc (bldc) motors and ac asynchronous motors. the igbt?s are configured in a 3-phase bridge with separate emitter connections for the lower legs for maximum flexibility in the choice of control algorithm. the power stage has a full range of protection functions including cross- conduction protection, external shutdown and under-voltage lockout functions. an internal comparator and reference connected to the over- current protection circuit allows th e designer to set the over-current protection level. features ? three-phase 10 a / 600 v igbt module with integrated drivers ? typical values : v ce (sat) = 1.8 v, v f = 1.5 v, e sw = 390 ? j at 10 a ? compact 29.6 mm ? 18.2 mm dual in-line package ? cross-conduction protection ? adjustable over-current protection level ? integrated bootstrap diodes and resistors ? enable pin ? thermistor typical applications ? industrial pumps ? industrial fans ? industrial automation ? home appliances figure 1. functional diagram www.onsemi.com package picture module spcm24 29.6x18.2 dip s3 marking diagram stk5q4u362j = specific device code a = year b = month c = production site dd = factory lot code device marking is on package underside ordering information device package shipping (qty / packing) STK5Q4U362J-E module spcm24 29.6x18.2 dip s3 (pb-free) 16 / tube
STK5Q4U362J-E www.onsemi.com 2 figure 2. application schematic STK5Q4U362J-E
STK5Q4U362J-E www.onsemi.com 3 figure 3. simplified block diagram
STK5Q4U362J-E www.onsemi.com 4 pin function description pin name description 1 gnd negative main supply 2 vdd +15 v main supply 3 hinu logic input high side gate driver - phase u 4 hinv logic input high side gate driver - phase v 5 hinw logic input high side gate driver - phase w 6 linu logic input low side gate driver - phase u 7 linv logic input low side gate driver - phase v 8 linw logic input low side gate driver - phase w 9 fault fault output 10 itrip current protection pin 11 enable enable input 12 rcin r, c connection terminal fo r setting fault clear time 13 th1 thermistor output 1 14 th2 thermistor output 2 17 nu low side emitter connection - phase u 18 nv low side emitter connection - phase v 19 nw low side emitter connection - phase w 20 w w phase output. internally connected to w phase high side driver ground 22 vbw high side floating supply voltage for w phase 26 v v phase output. internally connect ed to v phase high side driver ground 28 vbv high side floating supply voltage for v phase 32 u u phase output. internally connect ed to u phase high side driver ground 34 vbu high side floating supply voltage for u phase 38 vp positive bus input voltage note : pins 15, 16, 21, 23, 24, 25, 27, 29, 30, 31, 33, 35, 36, 37 are not present
STK5Q4U362J-E www.onsemi.com 5 absolute maximum ratings (notes 1, 2) 1. stresses exceeding those listed in the maximum ratings tabl e may damage the device. if any of these limits are exceeded, dev ice functionality should not be assumed, damage may occur and reliability may be affected. 2. refer to electrical characteristics, recommended operating ranges and/or application information for safe operating parameters. 3. this surge voltage developed by the switching operation due to the wiring inductance between vp and nu,nv,nw terminals. 4. v bs = vbu to u, vbv to v, vbw to w. 5. test conditions : ac 2500 v, 1 s recommended operating ranges (note 6) 6. functional operation above the stresses listed in the recommended operating ranges is not implied. extended exposure to stresses beyond the recommended operating ranges limits may affect device reliability. rating symbol conditions value unit supply voltage v cc vp to nu, nv, nw, surge < 500 v (note 3) 450 v collector-emitter voltage v ce max vp to u, v, w ; u to nu ; v to nv ; w to nw 600 v output current io vp, u, v, w, nu, nv, nw terminal current 10 a vp, u, v, w, nu, nv, nw terminal current, tc = 100 ? c 5 a output peak current iop vp, u, v, w, nu, nv, nw terminal current, pulse width 1ms 20 a gate driver supply voltages v dd ,v bs vbu to u, vbv to v, vbw to w, v dd to gnd (note 4) ? 0.3 to +20.0 v input signal voltage v in hinu, hinv, hinw, linu, linv, linw ? 0.3 to v dd v fault terminal voltage vfault fault terminal ? 0.3 to v dd v rcin terminal voltage vrcin rcin terminal ? 0.3 to v dd v itrip terminal voltage vitrip itrip terminal ? 0.3 to +10.0 v enable terminal voltage venable enable terminal ? 0.3 to v dd v maximum power dissipation pd igbt per 1 channel 31 w junction temperature tj igbt, gate driver ic 150 ? c storage temperature tstg ? 40 to +125 ? c operating case temperature tc ipm case temperature ? 20 to +100 ? c package mounting torque case mounting screw 0.6 nm isolation voltage vis 50 hz sine wave ac 1 minute (note 5) 2000 vrms rating symbol min typ max unit supply voltage v cc vp to nu, nv, nw 0 280 400 v gate driver supply voltage v bs vbu to u, vbv to v, vbw to w 12.5 15 17.5 v v dd v dd to gnd (note 4) 13.5 15 16.5 on-state input voltage v in (on) hinu, hinv, hinw, linu, linv, linw 3.0 5.0 v off-state input voltage v in (off) 0 0.3 pwm frequency fpwm 1 20 khz dead time dt turn-off to turn-on (external) 1 s allowable input pulse width pwin on and off 1 s package mounting torque ?m3? type screw 0.4 0.6 nm
STK5Q4U362J-E www.onsemi.com 6 7. product parametric performance is indicat ed in the electrical characteristics fo r the listed test conditions, unless otherwi se noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. electrical characteristics at tc = 25 ? c, v bs = 15 v, v dd = 15 v (note 7) parameter test conditions symbol min typ max unit power output section collector-emitter leakage current v ce = 600 v i ce - - 100 a collector to emitter saturation voltage ic = 10 a, tj = 25 ? c v ce (sat) 1.9 2.7 v ic = 5 a, tj = 100 ? c 1.6 - v diode forward voltage if = 10 a, tj = 25 ? c v f 1.5 2.2 v if = 5 a, tj = 100 ? c 1.2 - v junction to case thermal resistance igbt j-c(t) - - 4 ? c/w freewheeling diode j-c(t) - - 5.5 ? c/w switching time ic = 10 a, v cc = 300 v, tj = 25 ? c t on - 0.6 1.3 s t off - 1.0 1.6 turn-on switching loss ic = 10 a, v cc = 300 v, tj = 25 ? c e on - 300 - j turn-off switching loss e off - 90 - j total switching loss e tot - 390 - j turn-on switching loss ic = 10 a, v cc = 300 v, tj = 25 ? c e on - 360 - j turn-off switching loss e off - 110 - j total switching loss e tot - 470 - j diode reverse recovery energy ic = 10 a, v cc = 300 v, tj = 25 ? c (di/dt set by internal driver) e rec - 60 - j diode reverse recovery time trr - 160 - ns reverse bias safe operating area ic = 20 a, v ce = 450 v rbsoa full square - short circuit safe operating area v ce = 400 v scsoa 4 - - s allowable offset voltage slew rate u to nu, v to nv, w to nw dv/dt ? 50 - 50 v/ns driver section gate driver consumption current v bs = 15 v (note 4), per driver id - 0.07 0.4 ma v dd = 15 v, total id - 0.95 3 ma high level input voltage hinu, hinv, hinw, linu, linv, linw to gnd vin h 2.5 - - v low level input voltage vin l - - 0.8 v logic 1 input current v in = +3.3 v i in+ - 660 900 a logic 0 input current v in = 0 v i in- - - 3 a bootstrap on resistance ib = 1 ma rb - 110 - ? fault terminal sink current fault : on / vfault = 0.1 v iosd - 2 - ma fault clearance delay time rclr = 2 m ? , cclr = 1 nf fltclr 1.1 1.65 2.2 ms enable on/off voltage ven on-state voltage ven(on) 2.5 - - v ven off-state voltage ven(off) - - 0.8 v itrip threshold voltage itrip to gnd vitrip 0.44 0.49 0.54 v itrip to shutdown propagation delay t itrip - 1.1 - s itrip blanking time t itripbl 250 350 - ns v dd and v bs supply undervoltage positive going input threshold v dduv+ v bsuv+ 10.2 11.1 11.8 v v dd and v bs supply undervoltage negative going input threshold v dduv- v bsuv- 10.0 10.9 11.6 v v dd and v bs supply undervoltage i lockout hysteresis v dduvh v bsuvh - 0.2 - v
STK5Q4U362J-E www.onsemi.com 7 typical characteristics figure 4. v ce versus id for different temperatures (v dd = 15 v) figure 5. v f versus id for different temperatures figure 6. eon versus id for different temperatures figure 8. thermal impedance plot (igbt) figure 7. eoff versus id for different temperatures 0 200 400 600 800 0 2 4 6 8 10 12 14 16 18 20 eon [ j] ic [a] 0 50 100 150 200 250 0 2 4 6 8 101214161820 eoff [ j] ic [a] 0 5 10 15 20 0123 ic [a] vce [v] 0 5 10 15 20 0123 if [a] vf [v] figure 9. thermal impedance plot (frd) t j = 25 ? c t j = 100 ? c t j = 25 ? c t j = 100 ? c t j = 25 ? c t j = 100 ? c t j = 25 ? c t j = 100 ? c 0.0 0.2 0.4 0.6 0.8 1.0 0.0001 0.01 1 100 standardized rth [ ? c/w] pt [s] 0.0 0.2 0.4 0.6 0.8 1.0 0.0001 0.01 1 100 standardized rth [ ? c/w] pt [s] figure 10. turn-on waveform tj = 100 ? c, v cc = 400 v figure 11. turn-off waveform tj = 100 ? c, v cc = 400 v io:5a/div x:100ns/div vce: 100v/div io:5a/div x:100ns/div vce: 100v/div
STK5Q4U362J-E www.onsemi.com 8 applications information input / output timing chart figure 12. input/output timing chart notes 1. this section of the timing diagram shows the effect of cross-conduction prevention. 2. this section of the timing diagram shows that when the voltage on v dd decreases sufficiently all gate output signals will go low, switching off all six igbts. when the voltage on v dd rises sufficiently, normal operation will resume. 3. this section shows that when the bootstrap voltage v bs drops, the corresponding high side output (u or v or w) is switched off. when v bs rises sufficiently, normal operation will resume. 4. this section shows that when the voltage on itrip exceeds the threshold, all igbt?s are turned off. normal operation resumes later after the over-curr ent condition is removed. 5. after v dd has risen above the threshold to enable normal operation, the driver waits to receive an input signal on the lin input before enabling the driver for the hin signal. input / output logic table input output hin lin itrip enable high side igbt low side igbt u, v, w fault h l l h on (note 5) off vp off l h l h off on nu, nv, nw off l l l h off off high impedance off h h l h off off high impedance off x x h h off off high impedance on x x x l off off high impedance off
STK5Q4U362J-E www.onsemi.com 9 thermistor characteristics parameter symbol condition min typ max unit resistance r 25 tc = 25 99 100 101 k ? r 100 tc = 100 5.18 5.38 5.60 k ? b-constant (25 to 50 ) b 4208 4250 4293 k temperature range ? 40 +125 figure 4 thermistor resistance versus case temperature figure 5 voltage on circuit connected to thermistor (rth=39k, pull-up voltage 5v, see figure 2) figure 13. thermistor resistance versus case temperature figure 14. thermistor voltage versus case temperature conditions : rth = 39 k ? , pull-up voltage 5.0 v (see figure 2) case temperature ( tc ) ? th to gnd volta g e characteristic
STK5Q4U362J-E www.onsemi.com 10 fault output the fault output is an open drain output requiring a pull-up resistor. if the pull-up voltage is 5 v, use a pull-up resistor with a value of 6.8 k ? or higher. if the pull-up voltage is 15 v, use a pull-up resistor with a value of 20 k ? or higher. the fault output is triggered if there is a v dd undervoltage or an overcurrent condition. undervoltage lockout protection if v dd goes below the v dd supply undervoltage lockout falling threshold, the fault output is switched on. the fault output stays on until v dd rises above the v dd supply undervoltage lockout rising threshold. after v dd has risen above the threshold to enable normal operation, the driver waits to receive an input signal on the lin input before enabling the driver for the hin signal. overcurrent protection an over-current condition is detected if the voltage on the itrip pin is larger than the reference voltage. there is a blanking time of typically 350 ns to improve noise immunity. after a shutdown propagation delay of typically 1.1 ? s, the fault output is switched on. the fault output is held on for a time determined by the resistor and capacitor connected to the rcin pin. if rclr = 2 m ? and cclr = 1 nf, the fault output is switched on for 1.65 ms (typical). the over-current protection threshold should be set to be equal or lower to 2 times the module rated current (io). an additional fuse is recommended to protect against system level or abnormal over-current fault conditions. capacitors on high voltage and v dd supplies both the high voltage and v dd supplies require an electrolytic capacitor and an additional high frequency capacitor. enable pin the enable terminal pin is used to enable or shut down the built-in driver. if the voltage on the enable pin rises above the enable on-state voltage the output drivers are enabled. if the voltage on the enable pin falls below the enable off-state voltage, the drivers are disabled. minimum input pulse width when input pulse width is less than 1 s, an output may not react to the pulse. (both on signal and off signal) calculation of bootstrap capacitor value the bootstrap capacitor value cb is calculated using the following approach. the following parameters influence the choice of bootstrap capacitor: ? vbs : bootstrap power supply. 15 v is recommended. ? qg : total gate charge of igbt at v bs = 15 v. 45 nc ? uvlo : falling thre shold for uvlo. specified as 12 v. ? id max : high side drive consumption current . specified as 0.4 ma ? t onmax : maximum on pulse width of high side igbt. capacitance calculation formula: cb = (qg + i dmax * t onmax )/(vbs - uvlo) cb is recommended to be approximately 3 times the value calculated above. the recommended value of cb is in the range of 1 to 47 f, however, the value needs to be verified prior to production. when not using the bootstrap circuit, each high side driver power supply requires an external independent power supply. the internal bootstrap circuit uses a mosfet. the turn on time of this mosfet is synchronized with the turn on of the low side igbt. the bootstrap capacitor is charged by turning on the low side igbt. if the low side igbt is held on for a long period of time (more than one second for example), the bootstrap voltage on the high side mosfet will slowly discharge. figure 15. bootstrap capacitance versus t onmax 0.01 0.1 1 10 100 0.1 1 10 100 1000 bootstrap capacitance f t onmax [ms]
STK5Q4U362J-E www.onsemi.com 11 mounting instructions item recommended condition pitch 26.0 0.1 mm (please refer to package outline diagram) screw diameter : m3 screw head types: pan head, truss head, binding head washer plane washer dimensions (figure 16) d = 7 mm, d = 3.2 mm and t = 0.5 mm jis b 1256 heat sink material : aluminum or copper warpage (the surface that contacts ipm ) : ? 50 to 50 m screw holes must be countersunk. no contamination on the heat sink surface that contacts ipm. torque temporary tightening : 50 to 60% of final tightening on first screw temporary tightening : 50 to 60% of final tightening on second screw final tightening : 0.4 to 0.6 nm on first screw final tightening : 0.4 to 0.6 nm on second screw grease silicone grease. thickness : 50 to 100 m uniformly apply silicone grease to whole back. thermal foils are only recommended after care ful evaluation. thickness, stiffness and compressibility parameters have a strong influence on performance. figure 16. module mounting details: components; washer dr awing; need for even spreading of thermal grease recommended not recommended silicone grease
STK5Q4U362J-E www.onsemi.com 12 test circuits i ce u+ v+ w+ u- v- w- m 38 38 38 32 26 20 n 32 26 20 17 18 19 u+,v+,w+ : high side phase u-,v-,w- : low side phase v ce (sat) (test by pulse) u+ v+ w+ u- v- w- m 38 38 38 32 26 20 n 32 26 20 17 18 19 m 3 4 5 6 7 8 vf (test by pulse) u+ v+ w+ u- v- w- m 38 38 38 32 26 20 n 32 26 20 17 18 19 vbs=15v vbs=15v vbs=15v vdd=15v 34 32 28 26 22 20 2 1 a ice vce m n vbs=15v vbs=15v vbs=15v vdd=15v 34 32 26 22 20 2 1,10,n v vce(sat) ic m n m 5v figure 17. test circuit for i ce figure 18. test circuit for v ce (sat) figure 19. test circuit for vf
STK5Q4U362J-E www.onsemi.com 13 rb (test by pulse) u+ v+ w+ m 2 2 2 n 34 28 22 id vbs u+ vbs v+ vbs w+ vdd m 34 28 22 2 n 32 26 20 1 switching time (the circuit is a representative example of the low side u phase.) ib vdd=15v 6 7 2 1,3,4,5,10 v vb (rb) m n 5v 8 a m n id vd vbs=15v vbs=15v vbs=15v vdd=15v 34 32 28 26 22 20 2 1,10 cs vcc 38 17 6 input signal 32 ic input signal (0 to5v) 90% 10% ton toff io figure 20. test circuit for rb figure 21. test circuit for id figure 22. switching time test circuit
STK5Q4U362J-E www.onsemi.com 14 package dimensions unit : mm
STK5Q4U362J-E www.onsemi.com 15 on semiconductor and the on semiconductor logo are trademarks of semiconductor components industries, llc dba on semiconductor or its subsidiaries in the united states and/or other countries. on semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and othe r intellectual property. a listing of on semiconductor?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent-marking.pdf. on semiconductor reserves the right to make changes without further notice to any products herein. on semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does on semiconductor assume any liability arising out of the app lication or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. buyer is responsible for its products and applications using on semiconductor products, including compliance with all laws, regulations and safety require ments or standards, regardless of any support or applications information provided by on semiconductor. ?typical? parameters which may be provided in on semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. on semiconductor does not convey any license under its patent rights nor the rights of others. on semiconductor products are not designed, intended, or authorized for use as a critical component in life sup port systems or any fda class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended fo r implantation in the human body. should buyer purchase or use on semiconductor products for any such unintended or unauthorized application, buyer sh all indemnify and hold on semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, d amages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that on semiconductor was negligent regarding the design or manufacture of the part. on semiconductor is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resal e in any manner.

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